Building a Common Platform for Electronic-Photonic Integration

The MIT Microphotonics Center hosted a very successful IPSR-International 2026 Spring Meeting at MIT – “Building a Common Platform for Electronic-Photonic Integration”. Delivered in collaboration with MIT FUTUR-IC, MIT-MTL, and PhotonDelta, this year’s presentations, plenary sessions and Application Interest Group discussions brought together global industrial leaders, academic researchers, and R&D partners to accelerate the transition from lab to market.

Key highlights from the two-day event included:

🔹 System Requirements for AI & Datacenters: Keynotes from pioneers at Meta, NVIDIA, AMD, and Cisco mapping out the critical bandwidth density and performance metrics needed to scale future infrastructure.

🔹 Advancing CP-CIS: Shifting the Common Photonic Chiplet Integration Specification from a conceptual framework to a credible, industrially adoptable standard.

🔹 Design & Supply Chain Evolution: Driving EDA vendors to fully support cross-disciplinary electronic-photonic co-design while addressing the scaling bottlenecks of Co-Packaged Optics and High-Volume Manufacturing.

A huge thanks to our members, working group chairs, and the next-generation of manufacturing talent who joined us and help further define the next stage integration challenges and opportunities.

Stay tuned for an upcoming publication in the Microphotonics Center Newsletter detailing more highlights and roadmap session takeaways. All Microphotonics Center members will have access to cleared Meeting proceedings.

👉 Learn more about the roadmap and how to get involved with the Microphotonics Center and FUTUR-IC:

#IntegratedPhotonics #SemiconductorManufacturing #IPSR #FUTURIC #MITnano #WorkforceDevelopment #Photonics #AI #CoPackagedOptics

IKIM Hosts NSF-ATE NCAIST hands-on semiconductor packaging and testing bootcamp at MIT.nano

The MIT Initiative for Knowledge and Innovation in Manufacturing (https://microphotonics.mit.edu/) recently hosted 12 students from community colleges and four-year colleges across the Northeast for the NSF-ATE NCAIST hands-on semiconductor packaging and testing bootcamp at MIT.nano.

Over an intensive two days in the MIT LEAP (Lab for Education and Application Prototypes) at MIT.nano, students from MassBay Community College (MBCC), North Shore Community College (NSCC), Stonehill College, and SUNY Polytechnic stepped out of the classroom and directly onto the laboratory floor alongside MIT.nano staff and researchers.

The core curriculum focused on high-impact, workforce-ready skills, providing students with direct, practical experience across critical advanced semiconductor packaging infrastructure:

· Die Sawing – Substrate dicing and wafer singulation
· Die Bonding – Precision component placement and attaching die to substrates
· Wire Bonding – Establishing electrical interconnects using micro-fine wire leads
· Flip Chip Bonding – Advanced high-density packaging and face-down chip integration

By bridging physical fabrication with advanced simulation resources, these students are mastering highly specialized manufacturing, assembly, and testing pipelines required to build the future of electronic-photonic integration.

To complement these intensive physical lab sessions, the program integrates the Virtual Manufacturing (VM) Lab framework. This desktop VR simulation technology serves as an excellent foundational tool to help students (a) visualize not only photonic devices but also complex tool mechanics, (b) run digital process steps, and (c) deepen their technical understanding alongside live hardware instruction.

Thank you to the instructors, partners, and the students who put in the work at MIT.nano last week, to drive the semiconductor educational roadmap forward.

hashtag#Semiconductors hashtag#WorkforceDevelopment hashtag#MITnano hashtag#FUTURIC hashtag#LEAPLab hashtag#Cleanroom hashtag#Photonics hashtag#NCAIST hashtag#VMLab hashtag#AdvancedPackaging hashtag#IKIM

Launched: The Inaugural Microphotonics Center Quarterly Newsletter (Issue 1, 2026)

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Microphotonics Center

The Inaugural Newsletter

1st Quarterly Issue | 2026

Inside this Issue:


  • IPSR-I Roadmap Updates: Latest breakthroughs in E-P integration.

  • Upcoming Spring Meeting: May 13-14 registration details.

  • Member Spotlight: High-volume manufacturing compatibility and CPO.

Registration for the 2026 IPSR-I Spring Meeting 13-14 May is Now Open

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Save the Date: FUTUR-IC Presentations at IPSR-I, June 5

FUTUR-IC will present on the first day of the IPSR-International’s Spring 2025 Meeting, with the 9-5am session focusing on our semiconductor value chain innovation work.

The FUTUR-IC will give the following keynotes:

  • Keynote Session I: Hardware, Software and Architecture Convergence
    • Roadblocks and Solutions for Materials, Tools, and Processes; Comprehensive LCA accounting
  • Keynote Session II: Keynote Session II: Connectivity Requirements for AI Architectures
    • [Energy x Delay] Scaling for Data Centers and HPC: GPUs, Connections and Communications
  • Keynote Session III: Electronic-Photonic Package Level Integration
    • Solutions for Scaling Bandwidth Density, Energy and Cost: CPO, Connectors and Interfaces
  • Keynote Session IV: Packaging and Assembly: Polymer Technology Drivers
    • iNEMI Working Group Presentations and Panel Discussion

All are welcome to join a networking reception after the keynotes.

Location

MIT, Room 6-120, Cambridge MA